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lt6555 1 6555f applicatio s u descriptio u features typical applicatio u the lt 6555 is a high speed triple 2:1 video multiplexer with an internally fixed gain of 2. the individual amplifiersare optimized for performance with a double terminated 75 ? video load and feature a ?db 2v p-p bandwidth of 450mhz, making them ideal for driving very high resolu-tion video signals. separate power supply pins for each amplifier boost channel separation to 72db, allowing the lt6555 to excel in many high speed applications. while the performance of the lt6555 is optimized for dual supply operation, it can also be operated with a single supply as low as 4.5v. using dual 5v supplies, each amplifier draws only 9ma. when disabled, the amplifiers draw less than 500 a and the outputs become high impedance.the lt6555 is manufactured on linear technology? proprietary low voltage complementary bipolar process and is available in 24-lead ssop and ultra-compact 24-lead qfn packages. rgb amplifiers uxga video multiplexing lcd projectors 650mhz ?db small signal bandwidth 450mhz ?db 2v p-p large-signal bandwidth 120mhz 0.1db bandwidth high slew rate: 2200v/ s fixed gain of 2; no external resistors required 72db channel separation at 10mhz 50db channel separation at 100mhz ?0dbc 2nd harmonic distortion at 10mhz, 2v p-p ?0dbc 3rd harmonic distortion at 10mhz, 2v p-p low supply current: 9ma per amplifier 6.5ns 0.1% settling time for 2v step i ss 500 a per amplifier when disabled differential gain of 0.033%, differentialphase of 0.022 wide supply range: 2.25v (4.5v) to 6v (12v) available in 24-lead ssop and 24-lead qfnpackages 650mhz gain of 2 triple 2:1video multiplexer rgb multiplexer and line driver video amplitude transient response lt6555 v + v r ina g ina b ina r inb g inb b inb 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? select a/b 6555 ta01a agnd enable dgnd 75 ? 75 ? r out 75 ? 75 ? g out 75 ? 75 ? b out 2 2 2 , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. time (ns) 0 output (v) 0.6 1.0 1.4 1.81.6 16 6555 g21 0.2 0.2 0.4 0.8 1.2 0 0.4 4 8 12 21 8 6 10 14 20 v in = 0v to 700mv v s = 5v r l = 150 ? t a = 25 c downloaded from: http:///
lt6555 2 6555f total supply voltage (v + to v ) ............................ 12.6v input current (note 2) ........................................ 10ma output current (continuous) ............................. 70ma en to dgnd voltage (note 2) ................................. 5.5v sel to dgnd voltage (note 2) .................................. 8v output short-circuit duration (note 3) ............ indefinite operating temperature range (note 4) ... ?0 c to 85 c specified temperature range (note 5) .... ?0 c to 85 c order part number t jmax = 150 c, ja = 90 c/w consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. lt6555cgnlt6555ign absolute axi u rati gs w ww u package/order i for atio uu w (note 1) junction temperature ssop ................................................................ 150 c qfn .................................................................. 125 c storage temperature range ssop ................................................. ?5 c to 150 c qfn ................................................... ?5 c to 125 c lead temperature (soldering, 10 sec) ssop ................................................................ 300 c 12 3 4 5 6 7 8 9 1011 12 top view gn package 24-lead plastic ssop 2423 22 21 20 19 18 17 16 15 14 13 in1a dgnd in2a v ref in3a agnd1 in1b agnd2 in2b agnd3 in3b v v + ensel a/b v + out1v out2v + out3v v + v + g = +2 g = +2 g = +2 order part number uf part* marking 6555 lt6555cuflt6555iuf 24 23 22 21 20 19 7 8 9 top view 25 uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 v ref in3a agnd1 v in1b agnd2 v + out1v out2v + out3 in2adgnd in1a v + ensel a/b in2b agnd3 in3b v + v + v t jmax = 125 c, ja = 37 c/w, jc = 2.6 c/w exposed pad (pin 25) is v must be soldered to pcb electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 150 ? , c l = 1.5pf, v en = 0.4v, v agnd , v dgnd , v vref = 0v. symbol parameter conditions min typ max units v os input referred offset voltage v in = 0v, v os = v out /2 5 16 mv 24 mv i in input current ?7 45 a r in input resistance v in = 1v 100 400 k ? c in input capacitance f = 100khz 1 pf psrr power supply rejection ratio v s = 2.25v to 6v (note 6) 56 62 db i psrr input current power supply rejection v s = 2.25v to 6v (note 6) 1 4 a/v a v err gain error v out = 2v, nominal gain 2v/v 2.5 % a v match gain matching any one channel to another 0.33 % v out output voltage swing (note 7) 3.15 3.4 v 3.0 v downloaded from: http:///
lt6555 3 6555f i s supply current, per amplifier r l = 91 2 m a 14 ma supply current, disabled, per amplifier v en = 4v, r l = 47 500 a v en = open, r l = 42 500 a i en enable pin current v en = 0.4v ?00 ?5 a v en = 4v ?5 ?1 a i sel select pin current v sel = 0.4v ?0 ? a v sel = 4v ?0 ? a i sc output short-circuit current r l = 0 ? , v in = 1v 50 105 ma sr slew rate 1v on 2.5v output step (note 8) 1600 2200 v/ s ?db bw small-signal ?db bandwidth v out = 200mv p-p 650 mhz 0.1db bw gain flatness 0.1db bandwidth v out = 200mv p-p 120 mhz fpbw full power bandwidth 2v v out = 2v p-p (note 9) 250 350 mhz full power bandwidth 4v v out = 4v p-p (note 9) 175 mhz all-hostile crosstalk f = 10mhz, v in = 1v p-p ?2 db f = 100mhz, v in = 1v p-p ?0 db selected channel to unselected f = 10mhz, v in = 1v p-p ?0 db channel crosstalk f = 100mhz, v in = 1v p-p ?5 db channel select output transient ina = inb = 0v 200 mv p-p channel-to-channel select time ina = ?v, inb = 1v 8 ns from 50% sel to v out = 0v t s settling time 0.1% of v final , v step = 2v 6.5 ns t r , t f small-signal rise and fall time 10% to 90%, v out = 400mv p-p 520 ps dg differential gain (note 10) 0.033 % dp differential phase (note 10) 0.022 deg hd2 2nd harmonic distortion f = 10mhz, v out = 2v p-p 80 dbc hd3 3rd harmonic distortion f = 10mhz, v out = 2v p-p ?0 dbc electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, r l = 150 ? , c l = 1.5pf, v en = 0.4v, v agnd , v dgnd , v vref = 0v. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: this parameter is guaranteed to meet specified performance through design and characterization. it is not production tested.note 3: as long as output current and junction temperature are kept below the absolute maximum ratings, no damage to the part will occur.depending on the supply voltage, a heat sink may be required. note 4: the lt6555c is guaranteed functional over the operating temperature range of ?0 c to 85 c. note 5: the lt6555c is guaranteed to meet specified performance from 0 c to 70 c. the lt6555c is designed, characterized and expected to meet specified performance from ?0 c and 85 c but is not tested or qa sampled at these temperatures. the lt6555i is guaranteed to meetspecified performance from ?0 c to 85 c. note 6: in order to follow the constraints for 4.5v operation for psrr and i psrr testing at 2.25v, the dgnd pin is set to v , the en pin is set to v + 0.4v, and the sel pin is set to either v + 0.4v or v + 4v. at 6v and all other cases, dgnd is set to ground and the en and sel pins arereferenced from it. note 7: the v ref pin is set to 1v when testing positive swing and ?v when testing negative swing to ensure that the internal input clamps donot limit the output swing. note 8: slew rate is 100% production tested using both inputs of channel 2. slew rates of channels 1 and 3 are guaranteed through design and characterization. note 9: full power bandwidth is calculated from the slew rate: fpbw = sr/( ?v p-p ) note 10: differential gain and phase are measured using a tektronix tsg120yc/ntsc signal generator and a tektronix 1780r videomeasurement set. the resolution of this equipment is better than 0.05% and 0.05 . nine identical amplifier stages were cascaded giving an effective resolution of better than 0.0056% and 0.0056%. downloaded from: http:///
lt6555 4 6555f typical perfor a ce characteristics uw output voltage swingvs i load (output high) output voltage swingvs i load (output low) input bias currentvs temperature maximum output voltage swingvs v ref pin voltage en pin current vs en pin voltage input referred offset voltagevs temperature supply current per amplifiervs temperature supply current per amplifiervs supply voltage supply current per amplifiervs en pin voltage temperature ( c) ?5 supply current (ma) ?5 25 45 125 6555 g01 ?5 5 65 85 105 1210 86 4 2 0 v s = 5v r l = v in = 0v v en = 0v v en = 4v v en = 0.4v total supply voltage (v) 04 6555 g02 1 2 3 56789101112 supply current (ma) 1210 86 4 2 0 v en , v in , v dgnd , v sel = 0v t a = 25 c temperature ( c) ?5 ?5 offset voltage (mv) ?0 0 5 10 ?5 25 45 125 6555 g04 ? ?5 5 65 85 105 15 v s = 5v v in = 0v temperature ( c) ?5 input bias current ( a) ?0 ?5 ?0 105 6555 g05 ?5 ?0 ?0 ?5 25 65 ?5 125 5 45 85 ?5 0 ? v s = 5v v in = 1.5v v in = ?.5v v in = 0v en pin voltage (v) 0 en pin current ( a) 0 ?0?0 ?0 ?0 ?00?20 ?40 6555 g06 2 5 1 34 v s = 5v v dgnd = 0v t a = ?5 c t a = 25 c t a = 125 c v ref pin voltage (v) ? output voltage (v) 0 2 2 6555 g07 ?? ? 0 1 ?.5 ?.5 0.5 1.5 4 ? 1 ? 3 v s = 5v r l = 150 ? high swing low swing t a = 125 c t a = 125 c t a = 25 c t a = 25 c t a = 55 c t a = 55 c source current (ma) 0 output voltage (v) 3 4 5 80 6555 g08 2 1 0 10 20 30 40 50 60 70 90 100 v s = 5v v in = 2v v vref = 0v t a = 125 c v ref input clamping t a = 25 c t a = 55 c sink current (ma) 0 output voltage (v) ? ? 0 80 6555 g09 ? ? ? 10 20 30 40 50 60 70 90 100 v s = 5v v in = ?v v vref = 0v t a = 125 c v ref input clamping t a = 25 c t a = 55 c en pin voltage (v) supply current (ma) 6555 g03 1210 86 4 2 0 0 1.0 2.0 2.5 0.5 1.5 3.0 3.5 4.0 v s = 5v r l = v in = 0v t a = ?5 c t a = 125 c t a = 25 c downloaded from: http:///
lt6555 5 6555f typical perfor a ce characteristics uw frequency responsevs output amplitude gain flatness vs frequency crosstalk vs frequency frequency response withcapacitive loads harmonic distortion vs frequency input noise spectral density input impedance vs frequency input referred psrrvs frequency frequency (khz) 0.001 0.01 0.1 1 10 1 input noise voltage (nv/ hz or pa/ hz) 10 100 i n 1000 100 6555 g10 v s = 5v t a = 25 c e n 6555 g11 frequency (mhz) input impedance (k ? ) 0.01 0.1 10 100 1000 1 1000 100 10 1 0.1 v s = 5v v in = 0v t a = 25 c frequency (mhz) 20 power supply rejection ratio (db) 40 7010 30 50 60 0.001 0.1 1 10 100 6555 g12 0 0.01 psrr +psrr ?srr v s = 5v t a = 25 c frequency (mhz) 2 gain (db) 4 5 7 98 0.1 10 100 1000 6555 g13 0 1 63 1 v s = 5v r l = 150 ? t a = 25 c v out = 2v p-p v out = 4v p-p v out = 200mv p-p frequency (mhz) 6.00 normalized gain (db) 6.10 6.205.95 6.05 6.15 0.1 10 100 1000 6555 g14 5.90 1 in3a in1b in1a in2b in2a in3b v s = 5v v out = 200mv p-p r l = 150 ? t a = 25 c frequency (mhz) ? gain (db) 2 6 10 14 0.1 10 100 1000 6555 g15 ? 1 18 ? 0 4 8 12 16 v s = 5v v out = 2v p-p r l = 150 ? t a = 25 c c l = 4.7pf c l = 10pf c l = 0pf frequency (mhz) ?0 amplitude (db) ?0 0 ?00 ?0 ?0 0.1 10 100 1000 6555 g16 ?20 1 v s = 5v v out = 2v p-p r l = 150 ? t a = 25 c worst adjacent allchannels driven crosstalk vs frequency frequency (mhz) ?00 distortion (dbc) ?0 ?0 ?0 ?0 0.01 1 10 100 6555 g18 ?20 0.1 0 ?10 ?0 ?0 ?0 ?0 ?0 v s = 5v v out = 2v p-p r l = 150 ? t a = 25 c hd3 hd2 frequency (mhz) ?0 amplitude (db) ?0 0 ?00 ?0 ?0 0.1 10 100 1000 6555 g17 ?20 1 v s = 5v v in = 1v p-p r l = 150 ? t a = 25 c drive in a, select in b drive in b,select in a downloaded from: http:///
lt6555 6 6555f large-signal transient response typical perfor a ce characteristics uw gain error distribution gain matching distribution small-signal transient response large-signal transient response video amplitude transientresponse output impedance vs frequency frequency (mhz) 0.01 0.1 output impedance ( ? ) 10 1000 0.1 1 10 100 1000 6555 g19 1 100 disabled v en = 4v enabled v en = o.4v v s = 5v r l = 150 ? t a = 25 c time (ns) 0 output (v) 0.40.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 16 6555 g20 481 2 2 0 14 2 6 10 18 v in = 200mv p-p v s = 5v r l = 150 ? t a = 25 c time (ns) 0 output (v) 0.6 1.0 1.4 1.81.6 16 6555 g21 0.2 0.2 0.4 0.8 1.2 0 0.4 4 8 12 21 8 6 10 14 20 v in = 0v to 700mv v s = 5v r l = 150 ? t a = 25 c time (ns) ?.5 output (v) ?.5 0.5 1.5 ?.0 0 1.0 4 8 12 16 6555 g22 20 2 0 6 10 14 18 v in = 1v p-p v s = 5v r l = 150 ? t a = 25 c time (ns) 0 output (v) 43 2 1 0 ? ?? ? 16 6555 g23 4 8 12 20 14 2 6 10 18 v in = 2.5v p-p v s = 5v r l = 150 ? t a = 25 c gain error?ndividual channel (%) ?.5 percent of units (%) 25 30 35 1.5 6555 g24 15 0 ?.0 0.5 0 0.5 1.0 40 20 10 5 v s = 5v v out = 2v r l = 150 ? t a = 25 c gain matching?etween channels (%) ?.5 percent of units (%) 25 30 35 1.5 6555 g25 15 0 ?.0 0.5 0 0.5 1.0 40 20 10 5 v s = 5v v out = 2v r l = 150 ? t a = 25 c channel switching transient channel switching transient time (ns) 0 sel a/b (v) out (v) 42 5 0?.1 0.20.1 20 40 60 80 6555 g26 100 10 03 05 07 09 0 v s = 5v r l = 150 ? ina = 0vinb = 0v t a = 25 c time (ns) 0 sel a/b (v) out (v) 5 ?.5 0.5 1.5?.0 ?.5 0 1.0 40 6555 g27 4 2 3 1 0 10 20 30 100 50 60 70 80 90 v s = 5v r l = 150 ? inb = 300mhz, 1v p-p sine t a = 25 c ina = 0v downloaded from: http:///
lt6555 7 6555f in1a (pin 1): channel 1 input a. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.dgnd (pin 2): digital ground reference for enable pin. this pin is normally connected to ground.in2a (pin 3): channel 2 input a. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.v ref (pin 4): voltage reference for input clamping. this is the tap to an internal voltage divider that defines mid-supply. it is normally connected to ground in dual supply, dc coupled applications. in3a (pin 5): channel 3 input a. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.agnd1 (pin 6): analog ground for the 360 ? gain resis- tor of channel 1.in1b (pin 7): channel 1 input b. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.agnd2 (pin 8): analog ground for the 360 ? gain resis- tor of channel 2.in2b (pin 9): channel 2 input b. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.agnd3 (pin 10): analog ground for the 360 ? gain resistor of channel 3.in3b (pin 11): channel 3 input b. this pin has a nominal impedance of 400k ? and does not have any internal termination resistor.v (pin 12): negative supply voltage. v pins are not in- ternally connected to each other and must all be connectedexternally. proper supply bypassing is necessary for best performance. see the applications information section. v + (pins 13, 14, 24): positive supply voltage. v + pins are not internally connected to each other and must all beconnected externally. proper supply bypassing is neces- sary for best performance. see the applications informa- tion section. v (pin 15): negative supply voltage for channel 3 output stage. v pins are not internally connected to each other and must all be connected externally. proper supply bypass-ing is necessary for best performance. see the applications information section. out3 (pin 16): channel 3 output. it is twice the selected channel 3 input and performs optimally with a 150 ? load (a double terminated 75 ? cable). v + (pin 17): positive supply voltage for channels 2 and 3 output stages. v + pins are not internally connected to each other and must all be connected externally. proper supplybypassing is necessary for best performance. see the applications information section. out2 (pin 18): channel 2 output. it is twice the selected channel 2 input and performs optimally with a 150 ? load (a double terminated 75 ? cable). v (pin 19): negative supply voltage for channels 1 and 2 output stages. v pins are not internally connected to each other and must all be connected externally. proper supplybypassing is necessary for best performance. see the ap- plications information section. out1 (pin 20): channel 1 output. it is twice the selected channel 1 input and performs optimally with a 150 ? load (a double terminated 75 ? cable). v + (pin 21): positive supply voltage for channel 1 output stage. v + pins are not internally connected to each other and must all be connected externally. proper supplybypassing is necessary for best performance. see the applications information section. sel (pin 22): select pin. this high impedance pin selects which set of inputs are sent to the output pins. when thepin is pulled low, the a inputs are selected. when the pin is pulled high, the b inputs are selected. en (pin 23): enable control pin. an internal pull-up resistor of 46k defines the pin? impedance and will turnthe part off if the pin is unconnected. when the pin is pulled low, the amplifiers are enabled. exposed pad (pin 25, qfn only): the exposed pad is v and must be soldered to the pcb. it is internally connectedto the qfn pin 4, v . uu u pi fu ctio s (gn24 package) downloaded from: http:///
lt6555 8 6555f power suppliesthe lt6555 is optimized for 5v supplies but can be operated on as little as 2.25v or a single 4.5v supply and as much as 6v or a single 12v supply. internally, each supply is independent to improve channel isolation. do not leave any supply pins disconnected or the part maynot function correctly! enable/shutdown the lt6555 has a shutdown mode controlled by the enpin and referenced to the dgnd pin. if the amplifier will be enabled at all times, the en pin can be connected directly to dgnd. if the enable function is desired, either driving the pin above 2v or allowing the internal 46k pull- up resistor to pull the en pin to the top rail will disable the amplifier. when disabled, the dc output impedance will rise to approximately 360 ? through the internal feedback and gain resistors. supply current into the amplifier in thedisabled state will be: i vv k vv k s en =+ + + 46 80 it is important that the following constraints on the dgnd,en and sel pins are always followed: v + ?v dgnd 4.5v v en ?v dgnd 5.5v v sel ?v dgnd 8v in dual supply cases where v + is less than 4.5v, dgnd should be connected to a potential below ground, such asv . since the en and sel pins are referenced to dgnd, they may need to be pulled below ground in those cases.in single supply applications above 5.5v, an additional resistor may be needed from the en pin to dgnd if the pin is ever allowed to float. for example, on a 12v single supply, a 33k resistor would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. on dual 2.25v supplies, connecting the dgnd pin to v is the only way of ensuring that v + ?v dgnd 4.5v. the dgnd pin should not be pulled above the en pin sincedoing so will turn on an esd protection diode. if the en pin voltage is forced a diode drop below the dgnd pin, current should be limited to 10ma or less. the enable/disable times of the lt6555 are fast when driven with a logic input. turn on (from 50% en input to 50% output) typically occurs in less than 50ns. turn off is slower, but is typically below 500ns. channel select the sel pin uses the same internal threshold as the en pin and is also referenced to dgnd. when the pin is logic low, the channel a inputs are passed to the output. when the pin is logic high, the channel b inputs are passed to the output. the pin should not be floated but can be tied to dgnd to force the outputs to always be channel a or to v + (when less than 8v) to force the outputs to always bechannel b. truth table sel a/b en out 002 in a 102 in b x 1 off input considerationsthe lt6555 uses input clamps referenced to the v ref pin to prevent damage to the input stage on the unselectedchannel. three transistors in series limit the input voltage to within three diode drops ( ) from v ref . v ref is nomi- nally set to half of the sum of the supplies by the 40kresistors. a simplified schematic is shown in figure 1. to improve clamping, the pin? dc impedance should be minimized by connecting the v ref pin directly to ground in the symmetric dual supply case with a common modevoltage of 0v. while loaded output swing limits the useful input voltage range in that case, if the common mode voltage is not centered at ground or the input voltage exceeds plus or minus three diodes from ground, an external resistor to either supply can be added to shift the applicatio s i for atio wu u u downloaded from: http:///
lt6555 9 6555f applicatio s i for atio wu uu v ref voltage to the desired level. the only way to cover the full common mode voltage range of v + 1v to v + ?1v is to shift v ref up or down. note that on a single supply, the unclamped input range limits the output low swing to 2v(1v multiplied by the internal gain of 2). the v ref pin can also be directly driven with a dc source. bypassing the v ref pin is not necessary. the inputs can be driven beyond the point at which theoutput clips so long as input currents are limited to less than 10ma. continuing to drive the input beyond the output limit can result in increased current drive andslightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. layout and grounding it is imperative that care is taken in pcb layout in order to benefit from the very high speed and very low crosstalk of the lt6555. separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. if input or output traces must be run over a distance of several centimeters, they should use a con- trolled impedance with matching series and shunt resis- tances (nominally 75 ? ) to maintain signal fidelity. series termination resistors should be placed as close tothe output pins as possible to minimize output capaci- tance. see the typical performance characteristics sec- tion for a plot of frequency response with various output capacitors?nly 10pf of parasitic output capacitance before the series termination resistor causes 6db of peaking in the frequency response! low esl/esr bypass capacitors should be placed as close to the positive and negative supply pins as possible. one 4700pf ceramic capacitor is recommended for both v + and v ? supply busses. additional 470pf ceramic ca- pacitors with minimal trace length on each supply pin willfurther improve ac and transient response as well as channel isolation. for high current drive and large-signal transient applications, additional 1 f to 10 f tantalums should be added on each supply. the smallest valuecapacitors should be placed closest to the package. if the agnd pins are not connected to ground, they must be carefully bypassed to maintain minimal impedance over frequency. although crosstalk will vary depending upon board layout, a recommended starting point for bypass capacitors would be 470pf as close as possible to each agnd pin with a single 4700pf capacitor in parallel. v ref 40k40k 6555 f01 v + v in figure 1. simplified schematic of v ref pin and input clamping downloaded from: http:///
lt6555 10 6555f to maintain the lt6555? channel isolation, it is beneficialto shield parallel input and parallel output traces using a ground plane or power supply traces. vias between topside and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. see figures 6 and 7 for photos of an optimized layout. input expansion in applications with more than two inputs per channel, multiple lt6555s can be connected by several different methods. the simplest method is to connect the outputs after the 75 ? series termination, as shown in figure 2. the compromise of this approach is that the internal gainsetting resistors cause a 435 ? shunt across the 75 ? cable termination, resulting in increased gain error. applicatio s i for atio wu uu figure 3. disabled amplifiers load the cabletermination with 435 ? each figure 3 illustrates the loading effect of expanding thenumber of inputs. the resultant gain error can be calcu- lated by the following formula using n as the number of lt6555s: gain error (db) = 6db + 20log 435 n? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? 75 75 435 1 75 n db for example, two lt6555s would result in a gain error of?.74db per channel. three lt6555s (i.e., six red inputs, six green inputs and six blue inputs), would have a gain error of ?.4db. figure 2. two lt6555s build a 4-input router in1a in1b in1c in1d chip select 6555 f02 en lt6555 #1 75 ? a v = 2 lt6555 #2 74hc04 en 75 ? out a v = +2 75 ? cable 75 ? r275 ? 6555 f03 360 ? in1a in1c in1b in1d 75 ? 1/3 lt6555 #11/3 lt6555 #2 360 ? off 360 ? 360 ? off 360 ? 75 ? 75 ? 360 ? off 360 ? 360 ? on ? 435 n ?1 n = number of lt6555s in parallel .. . n downloaded from: http:///
lt6555 11 6555f applicatio s i for atio wu uu this systematic gain error can be significantly reduced bylowering the value of the 75 ? series termination resistors. the compromise of this approach is an increased depen-dence on the accuracy of the 75 ? shunt termination at the receiving end of the line. a table of values for 1% seriestermination resistors from n = 2 to n = 4 is shown below. number of devices (n) series r t 2 63.9 3 56.2 4 49.9 another approach that does not compromise gain accu-racy is to connect the outputs directly together before the series termination. in this case, there will be slightly increased output glitching and supply current spiking during the en pin switching, but the additional output loading will not increase the gain error, and the series termination resistors remain at their ideal value for ac response. see figure 4 for a scope photo showing the result of the outputs connected both before and after the series terminations, and figure 8 for a full schematic of a 4:1 rgb multiplexer with the output pins directly con- nected together. it is imperative that the output traces be as short as possible before the series termination in order to reduce capacitance and minimize ac peaking. figure 4. 4-input router switching with outputs directlyconnected and with outputs connected after 63.9 ? series termination esd protectionthe lt6555 has reverse-biased esd protection diodes on all pins. if any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. if the current is kept below 10ma, no damage to the devices will occur. time ( s) 0 multiplexed output (v) supply current (ma) ?.5 0 0.5 4 6555 f04 ?.0 1 2 3 0.5 1.5 2.5 3.5 1.5 1.0 0 50 i s i s + 100 150 v s = 5v v in(amp1) = 0.5v v in(amp2) = 0.5v r l = 150 ? outputsdirectly connected series 63.9 ? at each output typical applicatio u rgb multiplexer demo boardthe dc858a demo board illustrates optimal routing, bypassing and termination using the lt6555 as an rgb video multiplexer. the schematic is shown in fig- ure 5. all inputs and outputs are routed to have a charac- teristic impedance of 75 ? and 75 ? input shunt and output series terminations are connected as close to the part as possible. the board is fabricated with four layers withinternal ground and power planes. for ideal operation, a 75 ? load termination should be connected at the output. the lt6555? gain of 2 will compensate for the resultingdivider between the series and load termination resistors. figures 6 and 7 show the topside and bottom side board layout and placement. downloaded from: http:///
lt6555 12 6555f figure 5. demo board schematic 5 in1a 43 2 5 in2a 43 2 5 in3a 43 2 5 in1b 43 2 5 in2b 43 2 5 in3b 43 2 in1b agnd1 in3a v ref v ref in2a dgnd dgnd in1aagnd2 89 1011 12 7 6 5 4 3 2 1 1716 15 14 13 18 19 20 21 22 23 24 v + out2 v out1 in3b agnd3 in2bv v + v + v out3 v + sel sel en v + u1 lt6555cgn ext gnd 1 3 2 jp5 v ref jp12 bnc 6 dgnd 11 1 1 1 1 l1l1 l1 l1 l1 l1 z = 75z = 75 z = 75 z = 75 z = 75 z = 75 jp13jp14 jp5jp6 jp7 j3 banana jack float agnd 1 3 2 jp2 dgnd ext enable 1 3 2 jp1 control 1 3 v cc sel a/b ab dgnd 2 jp4 sel r7 20k j1 50 ? bnc en 5432 1 r1075 ? r1175 ? r1275 ? r475 ? r575 ? r675 ? 2 dual note: 470pf bypass capacitors located as close to pins as possible single agnd jp3 supply 3 1 e1 en e4 sel a/b e2 dgnd e5 v ref e3 agnd r850 ? opt z = 50 z = 50 en 5 out1 j9 1l2 l2l2 z = 75 r1 75 ? r2 75 ? r3 75 ? z = 75z = 75 11 j10j11 j4 banana jack v ee 6555 f05 43 2 5 out2 43 2 5 out3 v ee ?.3v to ?v 43 2 c14700pf c104700pf c110.33 f 16v c2470pf c3470pf c410 f 16v1206 c7470pf j2 banana jack v cc v cc 3.3v to 5v c80.33 f c54700pf c6470pf c910 f 16v1206 bnc 3 5432 1 r950 ? opt j8 50 ? bnc figure 6. demo board topside (ic removed for clarity) figure 7. demo board bottom side typical applicatio u downloaded from: http:///
lt6555 13 6555f si plified sche atic ww 360 ? 100 ? 770 ? 1k v + v + v + v v v ina en dgnd v v + sel to otherinput stages v ref v ref 40k 40k 100 ? inb v ref v ref select 46k bias to otheroutput stages v + out agnd 6555 ss v 360 ? 360 ? 360 ? (one channel shown) downloaded from: http:///
lt6555 14 6555f package descriptio u gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 ?.344* (8.560 ?8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 1617 18 19 20 21 22 23 24 15 14 13 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.19 ?0.25) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale downloaded from: http:///
lt6555 15 6555f uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) package descriptio u 4.00 0.10 (4 sides) note:1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?o be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 24 23 12 bottom view?xposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notchr = 0.20 typ or 0.35 45 chamfer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
lt6555 16 6555f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0405 500 ?printed in usa related parts typical applicatio u part number description comments lt1203 150mhz single 2:1 multiplexer single spdt video switch lt1399 300mhz triple current feedback amplifier 0.1db gain flatness to 150mhz, shutdown lt1675 250mhz triple rgb multiplexer 100mhz pixel switching, 1100v/ s slew rate, 16-lead ssop lt6550/lt6551 3.3v triple and quad video buffers 110mhz gain of 2 buffers in ms package lt6553 650mhz gain of 2 triple video amplifier performance similar to the lt6555 with one set of inputs, 16-lead ssop lt6554 650mhz gain of 1 triple video amplifier same pinout as the lt6553 but optimized for high impedance loads figure 8. 4:1 rgb multiplexer 2 lt6555 #1 v + in1a red 1 green 1 blue 1 red 2 green 2 blue 2 75 ? 75 ? in1b 2 in2a 75 ? 75 ? 75 ? 75 ? 75 ? in2b 2 in3ain3b sel out3 out2 out1 ?v 75 ? g out agndout1 out2 en 5v dgnd v v ref 2 lt6555 #2 v + in1a red 3 green 3 blue 3 red 4 green 4 blue 4 sel0sel1 75 ? 75 ? in1b 2 in2a 75 ? 75 ? 75 ? 75 ? in2b 2 in3ain3b sel out3 ?v agnd en 5v dgnd 6555 f08 v v ref 75 ? 75 ? r out 75 ? 75 ? b out nc75z14 sel1 00 1 1 sel0 01 0 1 output 12 3 4 downloaded from: http:///

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